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Results 1 to 25 of 1408

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SELF-ALIGNED SUBMICRON GATE DIGITAL GAAS INTEGRATED CIRCUITSLEVY HM; LEE RE.1983; ELECTRON DEVICE LETTERS; ISSN 0193-8576; USA; DA. 1983; VOL. 4; NO 4; PP. 102-104; BIBL. 6 REF.Article

DRY ETCHING AIDS IN REALIZATION OF VLS/SMITO H.1981; JEE, J. ELECTRON. ENG.; ISSN 0385-4507; JPN; DA. 1981; VOL. 18; NO 177; PP. 81-86Article

A 32-BIT VLSI CPU CHIPBEYERS JW; DOHSE LJ; FUCETOLA JP et al.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 537-542; BIBL. 3 REF.Article

ELECTRON BEAM LITHOGRAPHY MOVING INTO FOCUSFUKATSU Y; SAKIYAMA T.1981; JEE, J. ELECTRON. ENG.; ISSN 0385-4507; JPN; DA. 1981; VOL. 18; NO 177; PP. 92-95; BIBL. 4 REF.Article

SUBNANOSECOND SELF-ALIGNED I2L/MTL CIRCUITSTANG DD; NING TH; ISAAC RD et al.1980; IEEE TRANS. ELECTRON. DEVICES; ISSN 0018-9383; USA; DA. 1980; VOL. 27; NO 8; PP. 1379-1384; BIBL. 22 REF.Article

SELF-ALIGN IMPLANTATION FOR N+-LAYER TECHNOLOGY (SAINT) FOR HIGH-SPEED GAAS ICSYAMASAKI K; ASAI K; MIZUTANI T et al.1982; ELECTRON. LETT.; ISSN 0013-5194; GBR; DA. 1982; VOL. 18; NO 3; PP. 119-121; BIBL. 4 REF.Article

A NEW MOS INTEGRATED CIRCUIT FABRICATION USING SI3N4 FILM SELF-ALIGNMENT LIFTOFF TECHNIQUESYACHI T; YAMAUCHI N.1982; IEEE TRANS. ELECTRON. DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 2; PP. 243-247; BIBL. 11 REF.Article

A 3-NS 1-KBIT RAM USING SUPER SELF-ALIGNED PROCESS TECHNOLOGYSAKAI T; YAMAMOTO Y; KOBAYASHI Y et al.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 424-429; BIBL. 9 REF.Article

SUBNANOSECOND SELF-ALIGNED I2L/MTL CIRCUITSTANG DD; NING TH; ISAAC RD et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 444-449; BIBL. 22 REF.Article

A 400 PS BIPOLAR 18 BIT RALU USING ADVANCED PSASATO F; WAKAMATSU S; KUBOTA T et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 5; PP. 802-808; BIBL. 12 REF.Article

AN ADVANCED PSA TECHNOLOGY FOR HIGH-SPEED BIPOLAR LSINAKASHIBA H; ISHIDA I; AOMURA K et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 455-459; BIBL. 8 REF.Article

DSA MOS TRANSITOR AND ITS INTEGRATED CIRCUIT.HAYASHI Y; SEKIGAWA T; TARUI Y et al.1977; JAP. J. APPL. PHYS.; JAP.; DA. 1977; VOL. 16; SUPPL. 1; PP. 163-166; (CONF. SOLID STATE DEVICES. 8. PROC.; TOKYO; 1976)Conference Paper

FILM PROPERTIES OF MOSI2 AND THEIR APPLICATION TO SELF-ALIGNED MOSI2 GATE MOSFETMOCHIZUKI T; TSUJIMARU T; KASHIWAGI M et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 496-500; BIBL. 13 REF.Article

FULLY ION IMPLANTED DSA MOSIC.OHKURA I; OHMORI M; SHIMOTORI K et al.1977; JAP. J. APPL. PHYS.; JAP.; DA. 1977; VOL. 16; SUPPL. 1; PP. 167-171; BIBL. 11 REF.; (CONF. SOLID STATE DEVICES. 8. PROC.; TOKYO; 1976)Conference Paper

SWITCH-ON BEHAVIOUR OF MOS TRANSISTORS.BIERHENKE H; HERBST H.1977; ELECTRON. ENGNG; G.B.; DA. 1977; VOL. 49; NO 600; PP. 69-70Article

1.25 MU M DEEP-GROOVE-ISOLATED SELF-ALIGNED BIPOLAR CIRCUITSTANG DD; SOLOMON PM; NING TH et al.1982; IEEE JOURNAL OF SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 5; PP. 925-931; BIBL. 24 REF.Article

A SELF-ALIGNMENT PROCESS FOR AMORPHOUS SILICON THIN FILM TRANSISTORSKODAMA T; TAKAGI N; KAWAI S et al.1982; ELECTRON DEVICE LETTERS; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 7; PP. 187-189; BIBL. 12 REF.Article

QUADRUPLY SELF-ALIGNED MOS (QSA MOS) - A NEW SHORT-CHANNEL HIGH-SPEED HIGH-DENSITY MOSFET FOR VLSIOHTA K; YAMADA K; SAITOH M et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 4; PP. 417-423; BIBL. 22 REF.Article

PROCEDE IMPLANTE AUTOALIGNEDE BREBISSON M; TESSIER M.1980; ; FRA; DA. 1980; DGRST-77 7 0979; 25 P.: ILL.; 30 CM; BIBL. 3 REF.; ACTION CONCERTEE: COMPOSANTS ET CIRCUITS MICROMINIATURISESReport

SELF-ALIGNED TRANSISTOR WITH SIDEWALL BASE ELECTRODENAKAMURA T; MIYAZAKI T; TAKAHASHI S et al.1982; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 2; PP. 226-230; BIBL. 10 REF.Article

MOS DEVICE FABRICATION USING X-RAY LITHOGRAPHYSUZUKI K; MATSUI J; ONO T et al.1981; J. ELECTROCHEM. SOC.; ISSN 0013-4651; USA; DA. 1981; VOL. 128; NO 11; PP. 2434-2437; BIBL. 11 REF.Article

HBIP III: UNE NOUVELLE FILIERE TECHNOLOGIQUE BIPOLAIRE POUR CIRCUITS COMPLEXES DE HAUTES PERFORMANCESROCHE M.1983; REVUE TECHNIQUE THOMSON-CSF; ISSN 0035-4279; FRA; DA. 1983; VOL. 15; NO 1; PP. 253-288; ABS. ENG; BIBL. 13 REF.Article

SELF-ALIGNED ION IMPLANT MASKING FOR CMOS VLSI TECHNOLOGYPIMBLEY JM; GHEZZO M.1982; ELECTRON DEVICE LETT.; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 4; PP. 99-100; BIBL. 7 REF.Article

HIGH RESOLUTION TECHNIQUES FOR THE FABRICATION OF SMALL AREA JOSEPHSON TUNNEL JUNCTIONSHU EL; JACKEL LD; HOWARD RE et al.1981; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1981; VOL. 28; NO 11; PP. 1382-1385; BIBL. 9 REF.Article

A SELF-ALIGNED CONTACT MOS PROCESS FOR FABRICATING VLSI CIRCUITSKHAN MK; GODEJAHN GC JR.1981; J. ELECTROCHEM. SOC.; ISSN 0013-4651; USA; DA. 1981; VOL. 128; NO 6; PP. 1333-1335; BIBL. 1 REF.Article

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